The SM Bus is a two-wire bus. It is disposed at a motherboard of a computer and can communicate between low-bandwidth devices. The low-bandwidth devices at the motherboard includes a power chip, a temperature detecting chip, a fan control chip, a voltage detecting chip and so on.
FIG. 1 is a schematic diagram showing a conventional SM Bus system in a computer. The components connected to the SM Bus can be divided to master devices and slave devices. In FIG. 1, the SM Bus connects the first master device 12, the second master device 14, the first slave device 16, the second slave device 18, the third slave device 20, and the fourth slave device 22. Any of the master devices can communicate with any of the slave devices at the SM Bus.
FIG. 2 is a schematic diagram showing a start command protocol of the communication between the master devices and the slave devices of the SM bus. The start command protocol includes 20 bits. The 10th bit and the 19th bit are sent by the slave devices, and other bits are sent by the master devices. The first bit represents the start condition, next 7 bits stand represents the slave address, next one bit represents the read/write (R/W) command (“1” represents reading, and “0” represents writing), next 1 bit represents an acknowledge bit (“1” represents the acknowledge signal (ACK), and “0” represents the none acknowledgement status (NACK)), next 8 bits are the data bytes, next 1 bit is the acknowledge bit (“1” represents the ACK, and “0” represents the NACK), and the last 1 bit represents the stop condition.
The master device 12 and 14 can send a start command to the slave device 16, 18, 20 and 22 at the SM Bus using the protocol above. The start command includes an address representing a specific slave device at the SM bus. For example, the first master device 12 may send a start command at the SM Bus, and the first address of the start command represents the first slave device 16.
Since all the slave devices 16, 18, 20 and 22 are connected to the SM Bus, all of them can receive the start command sent by the first master device 12. When the slave device 16, 18, 20 and 22 receive the first address, the first slave device sends the ACK instantly, and the first slave device 16 starts to execute the command and communicates with the first master device 12. If the first slave device 16 cannot execute the command sent by the first master device 12 due to the busy state or the damage, the first slave device 16 sends the NACK. Thus, the command sent by the first master device 12 is interrupted, and the interruption command may result in an error, and the system is even unstable.
Except for the damage of the slave device, the command is interrupted mainly since the SM Bus connects two master devices at the same time. When the two master devices communicate to one slave device simultaneously, a bus collision happens. For example, the first master device 12 and the second master device 14 send the start commands at the same time, and the addresses of the start commands are the first addresses. At the moment, the first slave device sends the ACK to one master device (such as the first master device), but it cannot send the NACK to the second master device at the same time. Thus, the second master device cannot execute or stop executing the command in a predetermined time, which causes an error or a system crash.